Course Descriptions
Modeling and Synthesis of Digital Systems Using Verilog
Automatic design, synthesis, and verification of complex digital systems with Verilog are the main course objectives. This course uses Verilog to teach advanced register transfer level (RTL) design methodologies. Using Verilog for a design that consists of a hierarchy of components that include controllers, sequential and combinational parts is emphasized. Design description from transistor level to software interface will be discussed.
Students will learn details of hardware of processor architectures and their peripherals. Testbench development and assertion verification will be discussed. Students will learn to simulate verify, synthesize, and program their designs on an Altera development board using advanced Altera FPGAs. Specific topics covered are as follows:
- Verilog for synthesis
- Verilog testbenches
- RTL design methodology
- Combinational circuit description
- Sequential circuit description
- CPU design
- Hardware/Software interfacing
- Peripheral description in Verilog
Digital Systems Testing and Testable Design
This course discusses faults and fault modeling, test equipment, test generation for combinational and sequential circuits, fault simulation, memory testing, design for testability, built-in self-test techniques, boundary scan, IEEE 1149.1, and board and SoC test standards. Various fault simulation and ATPG methods including concurrent fault simulation, D-algorithm, and PODEM are discussed.
Controllability and observability methods such as SCOAP for testability analysis are discussed. Various full- and partial- scan methods are described and modeled in Verilog and tested with Verilog test benches. BIST architectures for processor testing, memory testing and general RT level hardware testing are described, modeled in Verilog and simulated and evaluated for fault coverage. The concept of virtual testers is discussed and Verilog modeling schemes for such applications are shown. Specific topics covered are as follows:
- Digital system test principles
- Fault modeling
- Fault simulation
- Test generation and compression
- Scan methods and scan design
- Boundary scan standard
- Built-In Self Test
- Virtual HDL based testers
- Memory testing
Methodologies for System Level Design and Modeling
This course discusses principles, methodologies and tools used for a modern hardware design process. Design flows and hardware languages needed for each stage of the design process are discussed. The use of transaction level modeling (TLM) for dealing with today's complex designs is emphasized.
The course starts with a discussion of the evolution of hardware design methodologies, and then discusses the use of C++ for an algorithmic description of hardware. SystemC and its TLM derivative and the role of SystemC in high level design will be discussed. In addition, RT level interfaces and the use of SystemC for this level of design will be covered. Timed, untimed, and approximately timed TLM models and modeling schemes will be presented. Use of TLM for fast design simulation, design space exploration, and high level synthesis will be discussed. TLM testing methods and testing of TLM based NoCs will be discussed. The course starts with a complete design project and exercises various parts of this design as methodologies, concepts, and languages are discussed. Specific topics covered are as follows:
- Levels of abstraction
- C++ for digital design
- SystemC RT level and above
- TLM methodology
- TLM timing aspects
- TLM channels
- TLM channels
- Mixed level design
- NoC TLM modeling
- System testing
Last modified: December 08, 2008 11:33:49